Integrated Dynamic Power Management Strategy with a Field Programmable Gate Array-Based Cryptoprocessor System for Secured Internet-of-Medical Things Networks
Journal
Technologies
ISSN
2227-7080
Publisher
MDPI AG
Date Issued
2025-02-04
Author(s)
Javier Vázquez-Castillo
Daniel Visairo
Ramón Atoche-Enseñat
Alejandro Castillo-Atoche
Renán Quijano-Cetina
Jaime Ortegón-Aguilar
Johan J. Estrada-López
Type
text::journal::journal article
Abstract
Advancements in electronics and sensor technologies are driving the deployment of ubiquitous sensor networks across various applications, including asset monitoring, security, and networking. At the same time, ensuring the integrity and confidentiality of data collected by sensor nodes is crucial to prevent unauthorized access or modification. However, the limited resources f low-power sensor networks present significant challenges for securing innovative Internet-of-Medical Things (IoMT) applications in complex environments. These miniature sensing systems, essential for diverse healthcare applications, grapple with constrained computational power and energy budgets. To address this challenge, this study proposes a dynamic power management strategy within a resource-constrained FPGA-based cryptoprocessor core for secure IoMT networks. The sensor node design comprises two main modules: an 8-bit reduced instruction set computer (RISC) and a cryptographic engine. These modules collaboratively manage their power consumption during the operational stages of data acquisition, encryption, transmission, and sleep mode activation. The cryptographic engine employs a pseudorandom number generator to generate a keystream for data encryption, utilizing direct sequence spread spectrum (DSSS) encoding to ensure secure communication. The experimental results demonstrate the effectiveness of the proposed dynamic power management strategy within the resource-constrained cryptoprocessor core. The sensor node achieves an average power consumption of 0.1 mW while utilizing 2414 logic cells and 5292 registers. A comparative analysis with other state-of-the-art lightweight sensor nodes highlights the advantages of our dynamic power management approach within the cryptoprocessor sensing system.
Table of contents
1. Introduction -- 2. Resource-Constrained RISC Cryptoprocessor Design -- 2.1. FPGA-Based RISC Processor Design -- 2.2. DSSS Cipher Engine Peripheral Architecture -- 2.3. Power Management Design -- 3. Implementation of the Dynamic Power Strategy -- 3.1. Low-Power Mode Configuration -- 3.2. Data Acquisition -- 3.3. Data Encryption and Transmission -- 4. Implementation Results -- 4.1. FPGA-Based Encryption/Decryption Validation Analysis -- 4.2. FPGA-Based DPMS Performance Analysis -- 4.2.1. Test 1: Hardware Speed Resource Analysis -- 4.2.2. Test 2: Power Consumption Estimation Analysis -- 4.2.3. Test 3: Cryptographic Randomness Performance Analysis -- 5. Discussion -- 6. Conclusions.